We open the galvanic isolation chip with a tiny transformer inside

I came across an advertisement for the sale of a tiny chip that provides 5 V isolating power ( galvanic isolation ). You supply 5 V on the one hand, and get 5 V on the other. It is noteworthy that the voltage difference between the two sides can reach 5000 V. A DC-DC converter and a tiny isolation transformer are installed in the chip, so there is no direct electrical connection between the sides. I was shocked that they were able to shove it all into a case the size of a nail, so I decided to look inside.

Many people complain about contextual advertising, but in this sense it ideally suited my interests. Chip UCC12050; specification . The chip produces 5 V, 3.3 V, 5.4 V, or 3.7 V - this can be selected using a resistor. Values ​​such as 5.4 and 3.7 V seem random, but they produce an additional 0.4 V, so that the voltage can be regulated with an LDO regulator [linear voltage regulator, characterized by a small voltage drop across the regulating element / approx. transl.]. Its power is small, only half a watt.

I got this chip from Texas Instruments. Robert Baruch from project5474 picked it up for me, boiling it in sulfuric acid at a temperature of 210 ° C. The epoxy case dissolved and a bunch of tiny components remained - they are shown below in the photo, with a one-cent coin for scale [coin diameter 19.05 mm / approx. transl.]. On top - two tiny silicon crystals, one for the primary circuit, the second for the secondary. Below them are two magnetized ferrite transformer plates. On the right is one of five pieces of fiberglass cloth. Below - a copper radiator, partially dissolved in the process.




Due to the internal structure of the chip, moisture can penetrate into it and remain inside. And when soldering the chip, moisture can evaporate, which is why the chip will burst like a popcorn seed. To avoid this, the chip was packaged in a waterproof bag with cards showing the level of humidity. The moisture sensitivity of the chip is the 3rd, which means that it needs to be soldered no later than a week after being removed from the package - otherwise it will need to be baked first.

Also in the chip were two octagonal copper coils - transformer windings. The photo below shows the remains of one of them. These are probably copper tracks on tiny printed circuit boards. Fiberglass is the remnants of these boards after the dissolution of the epoxy. Apparently, the winding consisted of several conductors running in parallel.



To understand how the components are interfaced, I studied Texas Instruments patents and found a similar galvanic isolation chip (below). Pay attention to the structure of crystals and coils. A key feature of the patent is that the contacts are raised inside and the crystals are mounted upside down. This improves the electromagnetic isolation from the circuit board.



The chip body is made according to the type of SOIC , and the size is smaller than a nail. Below is a view of the chip - the crystals and the winding are made so small that they fit in the case (it would be interesting to look at it in section). It is approximately twice as thick as the standard SOIC enclosure to accommodate multiple transformer layers.


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There are two silicon crystals in the chip - one for the primary circuit receiving power, and the second for the secondary circuit supplying power. The photo below shows a secondary circuit crystal. A metal layer is visible on top of the chip; I think that in total, three metal layers are used to bond all the components there. Silicon is not visible in the photo, it is hidden under the metal. At the top left, the conductors are soldered to the crystal pads. There is much more metal on the left side of the chip than on the right; on the left side is the analog power electronics, therefore, conductors that support high currents are required there.



If you remove the metal layers (I alternated hydrochloric acid to remove metal and a special mixture for etchingto remove silicon dioxide), silicon will be visible below them (see below). Visible transistors, resistors and capacitors. The metal layer is visually not very similar to the silicon lying below, but some features are common.



One of the interesting features of the chip is the filling of voids for chemical-mechanical planarization(CMP). In production, the chip layers were polished to a flat state using this technology. However, areas without metal conductors are softer, and they would be too drained. To avoid this, empty areas are filled with a square grid, which guarantees a uniform level of polishing of the chip. The filler is visible in the photo below - these are squares located at an angle. The chip has many metal layers, and each of them has its own filler lying at its own angle (the angle does not allow the filler to line up with other components, which minimizes stray capacitance and inductance).


The logo on the primary crystal, surrounded by filler. P stands for primary.

At the bottom of the chip, under the metal layers, silicon also has a CMP filler. These squares are part of silicon, and the lines between them are filled with some kind of material, probably polysilicon . Although this grid is angled, the squares are parallel to the chip.



The diagram below shows a part of the crystal components. On the left are the power components connected to the transformer, on the right is the control logic.



The logic of the chip, apparently, consists of two blocks of standard cells, where each logical element is taken ready from the library, and the cells line up in a grid. The photo below shows a closeup logic. Each block is a MOS transistor, and they are connected by metal layers on top. The smallest details are about 700 nm wide - the wavelength of red light (so the picture is blurry). For comparison, the most advanced chips today are switching to the 5 nm manufacturing process - this is 140 times less.



A fairly large part of the chip area is occupied by capacitors, consisting of a metal layer lying on silicon and separated by a dielectric. Large square sections in the photo below are capacitors; the dielectric looks yellowish, reddish or greenish, depending on the thickness. They are connected by a metal layer forming larger capacitors. A square pattern is a CMP filler. I did not succeed in dissolving the dielectric - I suspect that it may be silicon nitride, and not silicon dioxide, from which most of the insulation between the layers is made.



The horizontal stripes on silicon below are resistors formed by impurities that increase the resistance of individual sections. The resistance is proportional to the length divided by the width, therefore, to obtain significant resistance, the resistors are made long and thin. By connecting the strips of resistors at the ends with a zigzag, you can get a resistor of even greater denomination.



The photo below shows part of the transistors of the chip. A wide range of different transistors is used on the chip, from large power transistors (bottom) to a collection of tiny logic transistors to the left of the “10 µm” label. All transistors are given on one scale, so that you appreciate the significant difference in size (there may be diodes).

Primary crystal

The photo below shows the primary silicon crystal. Some of the pins are connected to the chip on top. Part of the metal layer has been removed for the photo, and conductors are visible in these places. In the upper part of the chip there is an analog power circuit, mainly capacitors, and is covered with an almost uniform metal layer (I accidentally dropped the crystal during cleaning into the sewer, so there are not many photos left).



A close-up below shows a crystal in the process of removing a metal layer and a silicon oxide layer. Please note - some pieces of metal and polysilicon broke off from the crystal and turned at random angles. It is seen that the crystal structure is three-dimensional, in it many layers lie on top of each other. After removal of silicon oxide, the layer structure may fall away.

How does the chip work?

The basic concept of the chip is straightforward. It operates with a DC-DC converter with galvanic isolation. The primary side converts the incoming voltage into pulses, and transfers them to the transformer. The secondary side rectifies the pulses and provides an output voltage. Since there is a transformer between the primary and secondary sides, they do not have a direct electrical connection, and the voltage is electrically isolated. But the details of his work are not described in detail: there are many possible “ topologies ” for generating and rectifying pulses: a flyback converter , a forward-flow converter, a bridge converter. Another issue is related to output voltage control.

There are several ways to control the output voltage. A widespread approach is in which feedback is transmitted from the secondary side via an optocoupler , thanks to which the primary side can regulate the voltage. In another approach, the primary side uses a separate transformer to monitor the voltage. Apparently, it is impossible to use these options in this chip: there is no feedback path here, and the secondary side chooses the output voltage. An ineffective approach could be taken, and a linear voltage regulator should be placed on the secondary side to reduce the voltage to the desired value.

I have studied various TI patents, and I think that this chip uses a technology called “phase-shifted dual-active-bridge” (see below). The primary side uses an H-bridge of four transistors (left) to send positive and negative pulses to the transformer (in the middle). A similar H-bridge on the secondary side (right) converts the transformer output back to direct current. The H-bridge is used instead of diodes on the secondary side because it is possible to change the amount of transmitted energy by changing the timing. In other words, the voltage can be controlled by a phase shift between the primary and secondary bridges. Unlike most converters, neither the frequency of the pulses nor their width changes here.


Diagram from patent 10122367

Each H-bridge consists of four transistors: two n-channel and two p-channel MOS transistors. The photo below shows six large power transistors that occupy most of the secondary crystal. I studied their structure, and it seems to me that the two transistors on the right are n-channel MOSFETs, and the other four are p-channel MOSFETs. It turns out four transistors necessary for the H-bridge, and two more for other purposes.

Chip usage

I connected the chip through the breadboard, and it worked as promised. It is extremely easy to use - only a couple of filtering capacitors are needed, at the input and output. Although the crystals are full of capacitors, they are too small to filter. External capacitors have a higher capacitance. I applied 5 V to the input (bottom left) and got 5 V at the output (top right) that lit the LED. In power-related electronics, it is important to follow the guidelines for the arrangement of elements to avoid noise and oscillations. However, although my board did not satisfy any of them, the chip worked perfectly. I measured the output at 5 V and the noise was minimal.

Conclusion

When I saw a chip containing a full-fledged DC-DC transformer, I decided that there must definitely be some interesting technology inside it. Opening the case revealed its components to me, including two silicon crystals and tiny flat transformer windings. Studying the components and comparing them with Texas Instrument patents, I came to the conclusion that the chip uses the topology of a dual active bridge with a phase shift for energy transfer. Interestingly, this technology is gaining popularity with chargers for electric vehicles, although there we are talking about much higher energies.

The crystals turned out to be complex, with three layers of metal and small components that are not visible in the optical device. Usually, I study chips a few decades older, which are much easier to understand, so this article has more of my guesses than reverse engineering (that is, somewhere I could have made a mistake).