Design and manufacture of ternary microcircuits using the usual CMOS process technology

Many claimed that they build a ternary computer from discrete components, but some are developing and ordering ternary microcircuits right now :)



I developed and ordered my first ternary microcircuit (the same crystal was packed in 3 different sizes - DIP40, DIP28 and SOIC16) in 2015. Today it was my first and last experience of this kind, but there is a desire and strength to try again - taking into account the experience gained and with an eye on real usefulness such as ternary programmable logic and / or ternary microcontroller - something that immediately could be used.

And now about how actually I did it and what came of it. My threefold epic began at the end of 2004, when nedoPC on my forum of fans of retrocomputers and home-made electronicsdiscussions began on a balanced ternary number system and the possibility of building new computers based on it. Then the forum users began to search for materials on this topic on the network and many, to their surprise, learned that ternary computers were developed a long time ago and even were mass-produced - in particular, the Setun ternary computer, which has been produced since 1959, was designed by Nikolai Petrovich Brusentsov and a group of like-minded people in the computing center of Moscow State University and was quite widespread throughout the country.

It is important to understand that by the ternary number system we primarily mean “balanced” triple (balanced ternary), where three states -1.0, + 1 are used (and not at all 0.1.2 as many might think). And so we on the forum started trying various options for building ternary elements from available components - we tried comparators (with diodes):



bipolar transistors (with zener diodes):



optocouplers (with transistors):



and finally analog keys :



along the way I got some hybrids - for example, comparators, diodes and CMOS keys:



or bipolar transistors, optocouplers and CMOS keys:



(and in 2011 I even uploaded a videothe full triple adder, built on such hybrids, works :)

But in terms of simplicity (2 microcircuits, 4 capacitors, a comb of contacts) and speed (up to 2.5 MHz), the DG403 circuit exceeded all other options - in November 2010 I created TRIMUX - a dual ternary selector (multiplexer / demultiplexer):



Subsequentlyhaqreumade his version of this handkerchief on surface mount components and began to build the TRIADOR ternary computer on them (the architecture of which was also born in the discussions on the nedoPC forum ) - see here for more details .

So - by 2015, I had a firm conviction that the basis of the ternary circuitry should be the ternary selector on which to build EVERYTHING. But to get something less useful, you need hundreds of ternary selectors. I did not want to solder hundreds of trimuses, but I wanted to make my own ternary microcircuit - but how? FPGA is not a method - everything is binary inside (presenting a ternary signal with a pair of binary is boring and uninteresting). If you make a real chip, then only the usual CMOS process technology is available on which almost everything has been done in the last few decades (only the sizes of transistors change - they become smaller and smaller):



Buying a commercial chip development product was unrealistic (very expensive), so I Found Magic VLSI Open Source Package(there are assemblies for Linux and Windows), to which there are rules files, for example, according to the CMOS 0.5um process technology, on which at that time the American company MOSIS , working at the University of Southern California, was taking orders , and I focused on them, creating an official business in the USA because MOSIS does not work with individuals (in fact, I still tried to go to one European company, which also collects different designs on one silicon wafer, but in the end they refused to work with me).

For experiments, I first took the free simulator LTspiceIV (this is a Windows program that works great on Linux from under Wine). And I began to build there the usual (binary) CMOS circuits and test them on SPICE models of real PMOS and NMOS transistors (such models walk on the Internet and can often be found in online manuals on VLSI courses of American universities):





I noticed that in depending on how the inputs of the logic gate are connected, the threshold for its operation is shifted:



It turns out that if you take 3-input NAND blocks (for which the response threshold could shift to the right) and 3-input NOR blocks (for which the response threshold could shift to the left) and connect their inputs to the ground or power in a certain way, you can get the operation thresholds spaced so that to detect an intermediate voltage at the input - after receiving a regular logic signal, we can send it (and its inversion) to a CMOS key that can turn on or off the analog signal going through it (and this switch works in both directions):



As a result, I got such a circuit, which has several trigger thresholds:



This circuit has a control input S, which, when connected to ground, an intermediate voltage or power, connects the common signal C to the contacts N (negative), O (intermediate) or P (positive), respectively - in this case we consider the intermediate voltage as a signal zero , respectively, the ground of the microcircuit is -2.5V, and the power is + 2.5V. In the course of the work area, there are 2 holes that make random short circuit impossible if neighboring keys suddenly turn on at the same time as the active zones trigger (after all, the inputs of the ternary selector can be connected to ground or directly to the power supply) because these boundaries are made by “holes”:



Using wonderful video Magic tutorials ( here and here) I started drawing transistors - so that the trigger threshold is exactly in the middle, the size of the upper transistor (PMOS) should be about 2 times the size of the lower transistor (NMOS):



Magic allows you to save the drawn to the library and then allows you to create more complex circuits from the saved library components, connecting the blocks with metallization layers (of which there were 3 in this process):



The process rules allow you to pull out the entire SPICE model of the whole circuit and then this model can be simulated in ngspice (open source SPICE simulator, present for example among standard Debian Linux packages).

In the process of working on my library, I managed to find an interested group of people, consisting of citizens of different countries, who agreed to pay half of the production (the minimum lot is 40 crystals) in exchange for help with some ternary and quaternary schemes - as a result, the upper half of the crystal was occupied by some I probably have no right to talk about things, and the lower one had a module for selective testing of 16 basic circuits (on the left) and the ternary selector itself (on the right):



In total, this design had about 1,500 transistors located on a 2.2x2.2mm chip with 40 pads (10 on each side) 100x100um in size, and all the transistors, pads and signals were manually painted by me from scratch and I, of course, I didn’t miss the opportunity to write my nickname on the crystal under the same ternary selector indicating the year :)



It’s always nice to see your own name under the “small scope”, introducing yourself as a Lefty, shoeing a flea;)



Having handed over the design to production in June 2015, I got ready-made silicon crystals and 8 chips packed in DIP40 only in October:



After making sure that the microcircuit works as a whole, I added the remaining silicon crystals (sending them back) to the DIP28 (to give the children part of them) and SOIC16 cases where only the signals of the ternary selector stick out (it cost several thousand more):



For detailed testing, I I ordered a handkerchief for these soics, soldering one of the microcircuits there:



and took the oscillograms with a digital oscilloscope-prefix to the computer - the selector connected in the ternary buffer mode:



and in the ternary inverter mode:



Here the power was -5V ... + 5V (a little more than normal voltage 5V between the ground and the power supply recommended for CMOS 0.5um) and it can be seen that the thresholds of the slang have moved off, but in general the average voltage is quite determined for itself. The only problem with these chips isthey work only at frequencies up to 10 kHz :(

My assumption about the poor dynamic characteristics of these microcircuits is that I tried to independently fulfill the special requirement of the manufacturer - they required that all free places on the chip be filled with blocks with metal layers, etc. since their absence can be damaged when etched by neighboring designs located on the same plate, as a result I had to invent my own block filler:



which filled all the free spots on the crystal:



And it seems I forgot to connect it to the ground as a result, heaps of parasitic capacities, eating all the high frequencies, hung out on the crystal. Next time I’ll try to avoid this error, or maybe I’ll take a commercial product for work and use its libraries, because my selector can be made up of STANDARD binary components while working with ternary signals. It may be possible to find again an interested group of people who would agree to share the cost of the next batch (for example, one chip from the last batch will cost about three hundred bucks at cost). I look forward to opinions and comments from respected Khabrovites :)