More SoC, good and different. Intel opens AIB for developers and manufacturers

In late January, Intel joined the alliance of companies CHIPS (Common Hardware for Interfaces, Processors and Systems), engaged in the development of open solutions for microprocessor high-density systems SoC and SiP (System in Package). As an "entry fee", Intel provided its consortium of manufacturers and developers with its own Advanced Interface Bus (AIB) signal exchange standard .

AIB is a standard developed by order of DARPA (Defense Advanced Research Projects Agency); its first version was released in 2017. At the end of last year, Intel introduced the second generation of AIB and MDIO (Multi-Die I / O) technology built on its basis. The table below summarizes the characteristics of two generations of AIB and TSMC rival LIPINCON technology.



AIB describes the interface of the signal interaction between the crystals in a heterogeneous microsystem, which uses a parallel data transfer mechanism similar to that currently used in the DDR DRAM (for a detailed technical description of the technology, click here) Being a standard of the physical layer, it does not depend on the process technology, manufacturer, or method of packing crystals. This makes AIB ideal for sharing by the alliance of stakeholders as a connecting structure in different types of packaging, be it EMIB from Intel, CoWoS from TSMC, or any other 2.5D technology.


Members of the CHIPS Alliance

Intel AIB is now available for use by third parties without paying royalties, so the transfer of technology to members of the CHIPS alliance was the next step in its dissemination. Intel hopes that the availability of using AIB will stimulate the emergence of new hybrid microprocessor solutions (chipsets) based on CPU, GPU, FPGA and other components.

Further development and improvement of AIB will be carried out by a working group on interconnects within the consortium, which, naturally, will include Intel, the company will continue to work on the technology.