🚩 🧑🏿 👐🏽 The beginning of the war of technological processes: 5 nm and 3 nm 🕜 ⛹🏼 🏼

New transistor structures, new tools and processes appear on the horizon - and with them a lot of problems

Several factories are trying to bring 5-nm process technology to the market, but their customers have to decide whether to design new chips on current transistors, or switch to new ones created in the 3-nm process technology.

For the transition, you must either expand the current finFET by 3 nm, or implement the new gate-all-around FET, GAA FET] technology by 3 nm or 2 nm. GAA FET is the next evolutionary step compared to finFET, they work faster, but these new transistors are more complicated and more expensive to manufacture, and switching to them can be too painful. On the other hand, the industry is developing new technologies for etching, structuring, etc., in order to clear the way to these new technological processes.

The release dates for these GAA FETs vary from factory to factory. Samsung and TSMC are doing finFET at 7 nm, and this year they plan to remake finFET at 5 nm, as well as produce chips in a half-step range of 5 nm. Such technical processes will improve both the speed of operation and energy consumption.

With regard to 3 nm, then Samsung plans to jump over to FAN nanosheet in a year or two - a new type of GAA transistor. TSMC plans to release finFET at 3 nm for the first time. TSMC will release GAA at 3 nm or 2 nm as the next step, as many analysts and equipment suppliers think.

“TSMC speeds up the development of finFETs at 3 nm, which are shrunken versions of 5 nm,” said Handel Jones, IBS Director. - Production of the first test copies of finFET at 3 nm TSMC will begin in 2020. Industrial production is planned for the 3rd quarter of 2021, which is a quarter earlier than the start of the 3 nm process technology from Samsung. "GAA development at TSMC lags behind Samsung by 12-18 months, but an aggressive strategy for the release of finFET at 3 nm can compensate for this gap."

TSMC continues to evaluate its options at 3 nm, and plans may still change. While the company does not comment on the situation, but promises to soon reveal its plans for 3 nm. Nevertheless, the transition of TSMC to 3 nm finFET is a logical step. Switching to new transistors can adversely affect customers. But ultimately, finFET will be exhausted, so TSMC has no choice but to switch to GAA.

Other companies are also developing advanced processes. Intel, occasionally involved in commercial production, produces chips at 10 nm, studying 7 nm in the laboratory. Meanwhile, SMIC makes finFET at 16 nm / 12 nm, while exploring in the laboratory 10 nm / 7 nm.

All advanced processes require significant finance, and not all chips require 3 nm or other advanced technologies. Rising prices are forcing companies to explore other development options. Another way to get the benefits of scaling is with new types of advanced chip packages. Several companies are developing such cases.

Operating voltage of various technologies

Has scaling come to an end?

Chips consist of transistors, contacts and their connections. Transistors play the role of switches. Advanced chips can contain up to 35 billion transistors.

The connections on top of the transistor consist of tiny copper wires that conduct electrical signals between transistors. Transistors and wiring are connected by an intermediate middle-of-line (MOL) layer. MOL consists of tiny contacts.

Scaling integrated circuits (ICs), their traditional way of development, is to reduce the size of the ICs with each new manufacturing process and packing them on a monolithic crystal.

To this end, chip manufacturers every 18-24 months present a new process that provides an increasing density of transistor packaging. Each process is given a numerical name. Initially, these names were associated with the length of the transistor valve.

For each subsequent process, manufacturers scale transistor specifications by 0.7 times, which allows the industry to increase performance by 40% with the same power consumption and reduce size by 50%. Scaling chips allows you to release new, more functional electronic products.

The formula worked, and chip manufacturers gradually changed technological processes. But at the turn of 20 nm, a change occurred - traditional flat transistors have chosen their entire resource. Since 2011, manufacturers switched to finFET, which allowed them to scale devices further.

However, finFET is more expensive to manufacture. As a result, the cost of research and development has skyrocketed. Therefore, the periods of transition from one technical process to another have increased from 18 to 30 or more months.

Intel has followed the general trend of scaling 0.7 times. However, starting from 16 nm / 14 nm, other manufacturers have moved this formula, which introduced some confusion.

At this point, the numbering of technical processes began to blur and lost touch with the specifications of transistors. Today, these names are just marketing terms. “The designation of technological processes is becoming less meaningful and understandable,” said Samuel Vaughn, an analyst at Gartner. - For example, at 5 nm or 3 nm there is not a single geometric size equal to 5 or 3 nm. In addition, processes from different manufacturers are becoming more and more different. For the same process technology, chip performance differs between TSMC, Samsung and, of course, Intel.

Scaling slows down in advanced manufacturing processes. For a 7 nm process, the gate step of the transistor [contacted poly pitch, CPP] is 56-57 nm with a metal step of 40 nm, according to IC Knowledge and TEL. For 5 nm, the CPP is approximately 45-50 nm with a metallic pitch of 26 nm. CPP, a key metric for transistors, refers to the distance between source and drain contacts.

In addition, the ratio of cost and speed does not look like that at all, because of which many believe that Moore’s law has already outlived itself.

“Moore’s law is actually just an observation, which has become a self-fulfilling prophecy that keeps the semiconductor industry moving forward. The economic aspect of Moore’s law began to deteriorate with the rising cost of multiple patterning and extreme ultraviolet lithography (EUV), said Douglas Guerero, chief technology officer at Brewer Science. “New architectures and designs will provide an increase in computing power, but it will no longer be scalable.” This means that in the future, chips will increase computing power, but their cost will not necessarily decrease at the same speed as before. "

Scaling is not something that completely stops. AI, servers and smartphones require ever-faster chips and advanced manufacturing processes. “About ten years ago, some people asked: Who needs even more transistors? Some thought that there were no more ideas in the world about what to do with faster computers, except for completely exotic applications, ”said Aki Fujimura, director of D2S. - Today, for the Internet of things, lower cost, fairly good performance and integration capabilities outperform a simple increase in density. However, for the manufacture of faster and more economical chips, in which the cost of transistors will fall, faster transistors are required. "

Obviously, advanced technological processes are not needed for everything. For chips produced by well-established technological processes, there is a high demand. “This includes ICs for working with radio waves and OLED displays in smartphones, as well as ICs for power management, which are used in computers and solid state drives,” said Jason Vaughn, one of the presidents of UMC.

FinFET scaling

In the matter of chip scaling, manufacturers for years followed the same pattern, with identical types of transistors. In 2011, Intel switched to finFET at 22 nm, and then at 16 nm / 14 nm.

In finFET, current is controlled by placing valves on all three sides of the fin. FinFET has 2 to 4 fins. Each has its own specific width, height and shape.

The first-generation finFET from Intel at 22 nm had a fin pitch of 60 nm and a height of 34 nm. Then, at 14 nm, the pitch and height were the same, 42 nm.

Intel made fins taller and thinner to scale finFET. “Scaling finFET reduces the transverse dimensions of the device, increasing density over the area, and increasing fin height improves performance,” wrote Nerissa Draeger, director of university relations at Lam Research, on her blog.

At 10nm / 7nm process technology, chip makers went the same way with finFET scaling. In 2018, TSMC began production of the first 7nm finFETs, followed by Samsung. Intel last year after several delays began production at 10 nm.

In 2020, factory competition will increase. Samsung and TSMC are preparing 5 nm and various half-integer manufacturing processes. Studies are ongoing regarding 3 nm.

All processes are expensive. The cost of designing a 3 nm chip is $ 650 million - compare this to $ 436.3 million for a 5 nm device and $ 222.3 million for a 7 nm device. This is the cost of such development, after which a year later the technology goes into production.

Compared to 7nm, Samsung's 5nm finFET will give a 25% increase in logical area, and a 20% decrease in energy consumption or a 10% increase in speed.

In comparison, finMET 5 mm from TSMC offers “a speed of 15% more at the same power consumption or a 30% reduction in power consumption at the same speed, with a 1.84-fold increase in logical density,” said Joffrey Yep, Chief Executive Officer for advanced technology at TSMC.

In the technological processes at 7 nm and 5 nm, chip manufacturers have made major changes. To manufacture mission-critical features in chips, the two companies have moved from traditional 193 nm lithography to extreme ultraviolet lithography (EUV). EUV uses wavelengths of 13.5 nm, which simplifies the process.

But EUV does not solve all the problems of chip scaling. “Solving these problems requires a variety of technologies, not just scaling, including the use of new materials, new types of integrated non-volatile memory and advanced logic architectures, new etching approaches, innovations in the manufacture of cases and chiplet designs,” said Regina Fried, Managing Director of Technology at Applied Materials.

Meanwhile, behind the scenes, Samsung and TSMC are preparing their 3nm process options. In the past, chip makers followed the same path, but today their paths diverge.

“3 nm comes in different flavors, such as finFET and GAA,” Vaughn said. “This enables customers to choose various combinations of cost, density, power consumption and speed, so as to satisfy their needs.”

Samsung promises to introduce a nanometer sheet FET at 3 nm. TSMC is also working on them, but plans to extend the use of finFET to the next generation. “TSMC will have a 3 nm finFET in the third quarter of 2021,” Jones said. “TSA's GAA will appear in 2022–2023.”

Here customers of factories should weigh the pros and cons regarding cost and technical compromises. The finFET extension is a safe way. “Many customers see TSMC as the least risky producer,” Jones said.

However, GAA provides a slight increase in performance. “The GAA has a 3 nm lower threshold voltage and potentially 15-20% less power consumption compared to a 3 nm finFET,” Jones said. “However, the difference in speed will be at the level of 8%, since MOL and BEOL are the same.”

Backend-of-the-line (BEOL) and MOL are bottlenecks in advanced chips. MOL's problem is contact resistance.

BEOL is the production phase where the wiring is connected. Due to their gradual reduction, delays associated with capacitive resistance occur. FinFET and GAA use different transistors, but their connection schemes in the 3 nm manufacturing process are likely to be almost the same. Capacitive delays will harm both types of transistors.

There are other problems. finFET will exhaust its capabilities when the fin width reaches 5 nm. finFET at 5 nm / 3 nm manufacturing processes already abuts this limit.

In addition, finFETs at 3 nm can consist of a single fin, compared to two or more fins in other manufacturing processes. “To extend finFET by 3 nm, we will need special technologies that increase the power of a single fin and reduce spurious phenomena,” said Naoto Horiguchi, CMOS Director at Imec.

One way to extend finFET to 3 nm is to switch to germanium for the p-channel. finFET at 3 nm with high-bandwidth channels will help increase the speed of the chips, however, they will encounter certain integration problems.

Transition to nanosheets

Ultimately, finFET will no longer scale, and chip manufacturers will have to switch to new transistors, namely nanosheet FETs.

Nanosheet FETs began to gain momentum in 2017 when Samsung introduced the 3 nm Multi Bridge Channel FET (MBCFET). MBCFETs are nanosheet FETs. Test samples will begin to be produced this year, and industrial production will begin in 2022.

TSMC also works with nanosheet FETs, which are one type of GAA transistor. Nanosheet FETs provide a slight advantage for scaling finFETs at 5 nm, but they have several advantages.

Nanosheet FET is, in fact, finFET, laid to one side, and wrapped with shutters. A nanosheet consists of several separate thin horizontal sheets laid on top of each other. Each sheet is a separate channel.

Around each sheet is a gate, and the result is a ring transistor. Theoretically, nanosheet FETs provide higher performance with less leakage, since current is controlled from four sides of the structure.

Initially, there will be approximately four sheets per nanosheet FET. “The width of a typical nanosheet is 12 to 16 nm, and the thickness is 5 nm,” said Horiguchi.

This differs from the nano sheet finFET. FinFET has a limited number of fins, which limits the work of designers. “The advantage of a nanosheet is that it can be changed in width. Width can be selected at the request of the designer. This gives them some freedom. They can find the best option for the ratio of energy consumption and speed, ”said Horiguchi.

For example, a transistor with a wider sheet will have a larger excitation current. A narrow sheet allows you to make the device smaller with a smaller field current.

Nanoliths are associated with nanowire technology, in which wires serve as channels. Limiting the channel width limits the field current.

Therefore, nanosheet FET and gaining momentum. However, this technology and finFET at 3 nm have several problems. “FinFET problems are related to quantum control of fin width and fin profile. The problems of nanosheets are related to the p / n imbalance, the efficiency of the bottom sheet, the interlayers between the sheets, the control of the valve length, ”said Gene Kai, TSMC Deputy Director, during the presentation at IEDM.

Given all these difficulties, it will take some time to enter the technology of nanosheet FET. “The transition to new transistor architectures has many obstacles,” Guerrero said. “Definitely, this will require new materials.”

In the simplest version of the process, the fabrication of a nanosheet FET begins with the formation of a superlattice on a substrate. The epitaxial instrument places interleaved layers of a silicon-germanium alloy (SiGe) and silicon on a substrate. The stack will consist of at least three SiGe layers and three silicon layers.

Then, vertical fins are formed in the superlattice by means of structuring and etching, which requires very precise process control.

Then begins one of the most difficult stages - the formation of internal gaskets. First, the outer parts of the SiGe layers are embedded flush in the superlattice. This creates small recesses filled with dielectric. “Indoor gaskets are needed to reduce valve capacity,” Kai said. “Making them is an essential part of the process.”

And such technologies already exist - IBM and TEL have recently described a new etching technique, suitable for both internal gaskets and channel production. For this, isotropic dry etching of SiGe with a ratio of 150: 1 is used.

This technology allows you to get very accurate internal gaskets. “Making recesses in SiGe requires very selective lateral blind etching of the layers,” said Nicholas Loubet, R&D Manager at IBM.

Then the source and the drain are formed. After that, SiGe layers are removed from the superlattice by etching. Silicon layers or sheets constituting the channels remain. High-k materials

are placed in the structure , and finally, MOL compounds are formed, which gives the nanosheet.

This is a simplified description of this complex process. However, like any new technology, nanosheets may be prone to defects. Additional study and measurement of all steps is required.

“As with previous transitions between technologies, we see problems associated with the study and measurement of nanosheets,” said Chet Lenox, director of process management solutions at KLA. “Many defective conditions may appear both in the inner gaskets and in nanosheets. IP manufacturers need the exact sizes of individual nanosheets, not just the average size of each stack to reduce the variability of their manufacturing processes. ”

This also requires new technologies. For example, Imec and Applied Materials recently introduced scalpel scanning spreading resistance microscopy (s-SSRM) technology for ring closures. In s-SSRM technology, a tiny scalpel breaks a small part of the structure, and dopants can be added to this section.

Other options

As part of R&D, Imec is developing more advanced types of GAAs, such as CFETs and Forksheet FETs (forksheet FETs) that target 2 nm or less.

By that time, for most manufacturers, scaling IPs would become too expensive, especially in light of the diminished benefits in power consumption and speed. Therefore, advanced chip layouts are gaining more and more popularity. Instead of cramming all the functions into a single crystal, it is planned to break the devices into smaller crystals and integrate them into advanced enclosures.

“It all depends on the application,” said Rich Rice, senior vice president of business development at ASE. - We definitely see an increase in such attempts, even in technological processes that have gone deep into submicron sizes. This development will continue further. Many companies do this. They decide whether they can integrate the 5 nm chips, and whether they want to. They are actively looking for ways to break systems. ”

This is not so easy to do. Plus, there are several shell options with various tradeoffs - 2.5D, 3D-ICs, chipsets and fan-out.

Conclusion

Definitely, not everyone will need such advanced manufacturing processes. However, Apple, HiSilicon, Intel, Samsung and Qualcomm are not in vain counting on advanced technologies.

Consumers need the latest and greatest systems with increased performance. The only question is whether the new technologies will give any real advantages at an affordable price.